System level interconnect design for network-on-chip using interconnect IPs

Abstract

As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [1][5][6]. NoC uses Interconnect Intellectual Property (IIP) to connect different resources. In a bottom up approach, this paper first studies the NoC system parameters constrained by the interconnections. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed. At last, the main IIP modules are described and one possible transmission scheme is demonstrated and simulated.