System Level Design Methodology for System On Chips using Multi-Threaded Graphs

Abstract

Multi threaded graph (MTG) models are expressive in explicitly representing the concurrency, event synchronization, data sharing and timing constraint aspects of a system. Because of their rich expressiveness and visual appeal, MTGs are also useful in conceptualizing these aspects of a system on chip (SoC), before designing them. Each intellectual property block of a system can be captured into an MTG and composed together to represent the SoC. To facilitate a design methodology based on MTGs, we have created a flow starting from capturing the control flow and data flow features of an SoC in a visual modeling framework for MTGs and translating to a formal model for verification using the UPPAAL model checker. The visual modeling front-end for MTGs is developed using the generic modeling environment (GME) tool that helps catch modeling errors at early stages of the design due to the syntactic and semantic constraints of the metamodel. The MTG representation is translated into extended timed automata (XTA) format that can be accepted by UPPAAL model checker. By translating the MTG to UPPAAL, important timing constraints, synchronization, deadlock freedom, etc can be formally verified. We have experimented with two non-trivial case studies of an FIR filter model and RISC CPU model