System Level Design and Verification Using a Synchronous Language

Abstract

Synchronous languages such as Esterel, Lustre, Signal, and others were originally developed for safety-critical embedded software and compiled into C. They have recently been extended to hardware with new language features and compilers to RTL. Contrary to traditional HDL languages (Verilog, VHDL) and recent system-level languages (SystemC, System Verilog), they have well defined formal semantics, which facilitate bug avoidance using correct-by-construction compilation and verification techniques. The tutorial will demonstrate what the synchronous language offers for the modeling, design, analysis and implementation of systems that comprise hardware and software. It will be based on Esterel. Esterel models have proved to be useful for rapid design space exploration and verification at system level, without resorting to detailed implementation and slow bit-level event-based simulation. We show how to model control-dominated IP blocks at a higher level of abstraction and how to use the target C code or RTL in conjunction with other system-level tools. Case studies include examples of design space exploration by synthesizing equivalent hardware or software from the same Esterel description, with formal verification of safety properties such as bus protocol conformance. We conclude with a review of future research directions.