Abstract

A novel request-driven globally asynchronous locally synchronous (GALS) technique for the system integration of complex digital blocks is proposed. For this new GALS technique, an asynchronous wrapper compliant is developed and evaluated. This proposed GALS technique is applied to a baseband processor compatible with the wireless LAN standard IEEE 802.11a. The developed GALS baseband processor chip is fabricated and measured. Besides improvements of the system integration process, a 5 dB reduction in electromagnetic interference, 30% reduction in instantaneous supply current variation, and similar dynamic power consumption as in the synchronous baseband processor is achieved. Modern mobile communication devices contain highly complex digital structures. An ever-increasing system com- plexity is leading to growing challenges in the area of system integration, power management and noise reduction. In order to cope with these problems, different methods have been proposed. One of the most promising techniques at present is the globally asynchronous locally synchronous (GALS) methodology for system integration. The GALS methodology was first proposed over twenty years ago by Chapiro (1) , and in the last few years has regained in popularity with several new methods being developed. A GALS circuit consists of several modules. Each module works synchronously and is surrounded by an asynchronous wrapper (AW) that has an asynchronous interface to other modules. Together, a wrapper and its enclosed module form a GALS block. Most GALS propo- sals are based on a pausible clocking scheme as can be seen in the works of Muttersbach (2) , Moore et al. (3) , and Bormann and Cheung (4) . Those GALS proposals

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