Abstract
A system of 3-channel DPC (digital pulse compression) system based on FPGA is designed. Some experimental data and results analysis of this system are given. This method of implementing DPC has the advantages of high speed and high reliability. The basic principle of DPC is introduced firstly. Then the composition of a DPC system based on Virtex-II family FPGA and its operating principle is presented. On the basis of given scheme of system design, the design of match filter and clock synchronizing circuit are discussed in detail from engineering practice. At last, a group of experimental data is given for an example and theoretical analysis to experimental result is also done.
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