Abstract

Top-pinned perpendicular magnetic tunnel junctions featuring a synthetic antiferromagnet (SAF) have been extensively studied for spin-transfer-torque magnetic random-access memory (STT-MRAM). However, degraded device performance after annealing remains a problem for this design, and hinders integration with CMOS technology. This study instead uses a synthetic $f\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}o\phantom{\rule{0}{0ex}}m\phantom{\rule{0}{0ex}}a\phantom{\rule{0}{0ex}}g\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}t\phantom{\rule{0}{0ex}}i\phantom{\rule{0}{0ex}}c$ (SFM) pinning layer to enable high thermal tolerance in STT-MRAM stacks. Experiment and simulation confirm functionality in 20-nm devices, including current switching. The proposed design contributes significantly to the scalability of STT-MRAM, and enables future applications requiring a top-pinned stack.

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