Synthesizable verification IP to stress test system-on-chip emulation and prototyping platforms

Abstract

One of the biggest challenges today with Pre-silicon System-on-Chip verification is to stress out the SoC to uncover as many corner case design issues by injecting heavy real time data traffic into the system. The inherent efficiency and the performance of the Emulation and FPGA prototyping systems make them the ideal platforms to run these tests. A typical solution is to inject data traffic through protocol exercisers with proprietary hardware (vendor specific slow down solutions) which can bridge the emulated DUT with a real time device or use software API's with transaction based SCE-MI communication infrastructure. The need for a complex input output interface makes the former difficult to be used with all emulators / FPGA prototyping systems while SCE-MI communication infrastructure being protocol specific is a disadvantage. So, a synthesizable verification architecture compliant with SCE-MI 2.0 infrastructure through which the protocol specific traffic is injected through industry standard interfaces. i.e. PIPE (PCIe), UTMI (USB), MII (Ethernet) based on user configured stimuli has been designed and implemented. Being synthesizable, the verification environment can run in both emulation and prototyping platforms effectively stress testing the complete system.