Synthesis procedures for switching circuits represented Reed-Muller form over a finite field

Abstract

The synthesis of economical multilevel circuits for binary and multiple-valued switching circuits is described. The mode of function description is that provided by the algebra of finite fields and this leads to a highly modular form of circuit representation. A universal-logic tree composed of GF(q) adders and multipliers is used as a template on which to construct specific multilevel circuits. The paper describes methods for assigning the input variables to the network so as to reduce the complexity of the general tree by removing the redundant circuit elements. The resulting networks are invariably less costly than those from the direct synthesis of two-level sum-of-products expressions and they use only a restricted set of circuit elements.