Synthesis of time-optimal systolic arrays with cells with inner structure

Abstract

We consider synthesis of synchronous systolic arrays, where the cells in the array themselves are pipelined. Synthesis of synchronous hardware for a particular algorithm is done by scheduling: for each step in the algorithm it is specified where and when it is to take place. This can be seen as specifying a mapping from algorithm steps to a space-time. Once the mapping is determined, a synchronous hardware structure that supports it can be derived. For regular algorithms, linear space-time mappings yield systolic array implementations. We show that for these mappings the problem of minimizing the execution time, under some desired constraints on the resulting array, becomes an integer programming problem. When the constraints can be expressed as linear inequalities, optimization algorithms can be formulated and the optimization procedure can be automated. A number of interesting constraints, including pipelining constraints for the cells, can indeed be expressed as linear inequalities.