Abstract
Syntheses procedures for lattice digital filter structures which can be free of constant-input limit cycles are presented. As a result, the realizations derived, in most cases, maintain the desirable properties of the original lattice while being free of constant-input limit cycles. The symmetric lattice structures, which are amenable to efficient VLSI implementation, are considered regarding their freedom from zero-input and constant-input limit cycles. The pertaining syntheses procedures are presented. Experimental results are included to compare the several realizations discussed with respect to output roundoff noise and multiplier coefficients sensitivity.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
