Abstract
This paper presents a synthesis algorithm toy digital signal processing (DSP) processor design that uses data pipelining to achieve high throughput and low cost. The hardware resources, which are composed of function units, register units, bus units, and memory units in an executing model, are described. Under the constraints in the resource library, the DSP data is read in as a control data flow graph. The resources selection, mapping, and sharing are conducted based on our algorithm. The experimental and comparative results are discussed.
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