Abstract
The advancing complexity of contemporary microelectronics has motivated research in high-level and system synthesis (HLS). Formal and intelligent HLS techniques are presented in this contribution, thus the generated implementation is correct-by-construction. These intelligent techniques include RDF (Resource Description Framework) and logic relations, along with automatic implementation options and they are employed for the transformations of a hardware compiler. The proposed toolset utilizes compiler-generators, RDF rules and logic programming in combination with XML validation of the internal state of the compiler. These intelligent and formal techniques make the whole transformation from source code to implementation, formal. The HLS tool is enhanced with the Parallel, Abstract Resource – Constrained Scheduler, which aggressively optimizes the initial state schedules, into maximally parallelized ones. A number of custom options are applied by the user of this toolset, in order to automatically compile selected testcases from real-world applications which prove the usability of the embedded scheduler and the formal compilation of the intelligent HLS compiler.
Highlights
Digital microelectronics found in embedded, high-performance and portable computing systems have highly complex components, design hierarchy and interconnections
During the last couple of decades, commercial and academic organisations have invested in high-level and system synthesis (HLS) and optimisation techniques, so as to achieve design automation, quality of implementations and short specification-to-product times [1,2]
Experienced programmers can use the CCC toolset, to implement very complex hardware designs in a few hours, whereas this takes usually more than 6 months of traditional development and verification time. This is due to the use of formal logic programming and Resource Description Framework (RDF) validation techniques embedded in the intelligence of the CCC synthesizer
Summary
Digital microelectronics found in embedded, high-performance and portable computing systems have highly complex components, design hierarchy and interconnections. This XML instance models one PARCS state of design Module_1, with three scheduled operations in parallel and with no conditional operations or transitions Both the logic and the XML views of IPF are extracted automatically by the front-end and back-end compilation phases, and they are validated in both logic programming and XML views. Experienced programmers can use the CCC toolset, to implement very complex hardware designs in a few hours, whereas this takes usually more than 6 months of traditional development and verification time This is due to the use of formal logic programming and RDF validation techniques embedded in the intelligence of the CCC synthesizer. All of the VHDL modules for the FIR filter and the RSA cryptoprocessor have been simulated ( due to the formal nature of the CCC tool, not necessary) and the results coincided with the results of the ADA verification testbenches
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