Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

Abstract

In this paper we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free and completely testable. Making an asynchronous two-level circuit hazard-free usually requires the introduction of either redundant or non-prime cubes, or both. This adversely affects its testability. However, using extra inputs, which is seldom necessary, and a synthesis for testability method, we convert the two-level circuit into a multi-level circuit which is completely testable. To avoid the addition of extra inputs as much as possible we introduce new exact minimization algorithms for hazard-free two-level logic where we first minimize the number of redundant cubes and then minimize the number of non-prime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.