Synthesis of an architecture for a clustered multiprocessor network

Abstract

The design and performance evaluation of a bus oriented clustered multiprocessor network have been reported earlier. In this paper, the datapath and control realization of the system is presented. Hardware realization is achieved partially by using a computer-aided design approach starling from a behavioural description of the network using a C-based hardware description language. Some of the datapath optimization and realization of the controller using the standard cell approach have been carried out manually for better design compaction.