Abstract
The article presents a technology for developing a terminal device for a multiplexed serial interface for data exchange to FPGA. The development was carried out using the System Verilog hardware description language. To meet demanding requirements. presented to this interface in terms of transmission speed, as well as the duration of transmitted and received bits of information, the device includes a built-in signal duration analyzer, which can also be used to exclude the influence of a part of the impulse noise that “leaked” through the input high-pass filter. The presented device has passed the verification of the main operating modes in the ModelSim-Altera software environment.
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