Synthesis of a narrow-band Low Noise Amplifier in a 180 nm CMOS technology using Simulated Annealing with crossover operator

Abstract

This paper presents the accurate synthesis of a narrow-band CMOS Low Noise Amplifier (LNA) using an optimization-based approach. Multi-objective information and the corners of the fabrication process are used in the synthesizer to simultaneously optimize impedance matching, performance parameters and circuit robustness. The synthesis approach combines the Simulated Annealing algorithm with the crossover operator and an automatic weight adjustment technique. This combination allows the optimizer to escape local minimums and therefore successfully achieve the LNA specifications. Two solutions of the synthesis are presented and the performance is verified through simulations using a 180 nm CMOS process. The first 2.45 GHz LNA solution achieved a Noise Figure of 1.95 dB, a S21 of 13.6 dB, a S11 of -17 dB, draining a 4.6 mA current. The second solution, which starts from the final first solution and adds a linearity constraint, achieved a Noise Figure of 2.04 dB, a S21 of 12.89 dB, a S11 of -25 dB, a PIIP3 of -7.8 dBm with a current of 4.1 mA. The results indicate the efficiency of the technique to synthesize LNAs, providing solutions comparable to similar presented in the literature.