Synthesis for Logic-in-Memory Computing Using RRAM

Abstract

This chapter presents a comprehensive approach for the synthesis of resistive in-memory computing circuits using Binary Decision Diagrams (BDDs), And-Inverter Graphs (AIGs), and the recently proposed Majority-Inverter Graphs (MIGs) for logic representation and manipulation. The proposed approach allows to perform parallel computing on a multi-row crossbar architecture for the logic representations of the given Boolean functions throughout a level-by-level implementation methodology. The chapter also provides alternative implementations utilizing two different logic operations enabled by RRAM devices. For each representation, optimization algorithms are proposed with respect to the number of RRAM devices and computational steps, addressing area and delay of the resulting implementations, respectively.