Synthesis and Analysis of Optimal Order Butterworth Filter for Denoising ECG Signal on FPGA

Abstract

This paper focuses on the synthesis of the design of optimal order Butterworth filter for denoising ECG signal on Field Programmable Gate Array platform. A summary of its resource utilization, the timing and power consumed are presented after synthesis and simulation. This is achieved by conversion of MATLAB code of designed digital filter into Verilog code using the HDL command-line interface. Spartan-6 FPGA (XC6SLX75T with 3FGG676 package) is used as a target device. Xilinx Power Estimator 14.1 tool used to estimate power consumed by digital design. Further, the complexity of the filter structure is also determined on the FPGA platform for its suitability of a hardware efficient filter design. The results suggest that the FPGA based Butterworth filter design for denoising ECG signal reduces the complexity and cost by reducing the number of multipliers and adders, which occupy a small portion of the chip area and consume low power than in MATLAB, hence are suitable for ECG portable device.