SynDFG: Synthetic dataflow graph generator for high-level synthesis

Abstract

Dataflow graphs obtained from benchmark applications depend on the compiler used and its settings. This makes comparison of results in high level synthesis research using such dataflow graphs difficult. Therefore, a synthetic dataflow graph generator for generating dataflow graphs of any size from a few tens of nodes to thousands of nodes for research in high level synthesis is presented. The user has the flexibility to specify number of nodes and set node attributes like node type (operation type), in-degree and the maximum and the minimum parallelism in each control step. The generated dataflow graphs can be used for research in scheduling, allocation and hardware binding. Sharing of input parameters among researchers will allow generation of identical synthetic graphs on identical platforms thus facilitating easier and more meaningful comparison of results. The concept of Biased Dataflow Graphs (BDFG) is introduced where operations of certain types are large in number. These provide the required granularity in operations, exploitation of inherent parallelism and option to explore the area space in modern FPGAs consisting of LUTs, BRAMs and DSP slices. The generated graphs overcome these limitations in the two existing methods: Task Graphs for Free (TGFF) and Synchronous Dataflow Graphs for Free (SDF3).