Abstract
This work presents a producer-consumer link between two independent clock domains. The link allows for metastability-free, low-latency, high-throughput communication by slight adjustments to the clock frequencies of the producer and consumer domains steered by a controller circuit. Any such controller cannot deterministically avoid, detect, nor resolve metastability. Typically, this is addressed by synchronizers, incurring a larger dead time in the control loop. We follow the approach of Friedrichs et al. (TC 2018) who proposed metastability-containing circuits. The result is a simple control circuit that may become metastable, yet deterministically avoids buffer underrun or overflow. More specifically, the controller output may become metastable, but this may only affect oscillator speeds within specific bounds. In contrast, communication is guaranteed to remain metastability-free. We formally prove correctness of the producer-consumer link and a possible implementation that has only small overhead. With SPICE simulations of the proposed implementation we further substantiate our claims. The simulation uses 65nm process running at roughly 2GHz.
Highlights
L INKS that enable communication between different clock domains are an important ingredient in every GloballySynchronous Locally Asynchronous (GALS) system [1]
Previous digital controller designs resort to different methods to deal with metastability: clock-masking [2], clockpausing [3], [4], or adding synchronizers to maintain a realistic mean time between failures (MTBF) of the link [2], [5]–[8]
There is a large body of work on links between clock domains, motivated by their central importance in GloballySynchronous Locally Asynchronous (GALS) designs
Summary
L INKS that enable communication between different clock domains are an important ingredient in every Globally. Previous digital controller designs resort to different methods to deal with metastability: clock-masking [2], clockpausing [3], [4], or adding synchronizers (while sacrificing latency) to maintain a realistic (yet finite) mean time between failures (MTBF) of the link [2], [5]–[8]. Downsides of these approaches are that synchronized fill level flags are inherently “stale” by the time they affect the system. PERFORMANCE AND HARDWARE OVERHEAD (BUFFER SIZE N , GATES, FLIP-FLOPS, OSCILLATOR TYPE) OF THE PROPOSED CONTROLLER WITH A TUNABLE 2.0 TO 2.3 GHz OSCILLATOR, [6], AND [10]
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More From: IEEE Transactions on Circuits and Systems I: Regular Papers
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