Abstract
The invention discloses a synchronization time-division multiplexing bus communication method adopting a serial communication interface. Data receiving lines and data delivery lines of a host machine and slave machines are all connected with a bus respectively. The method is that each slave machine receives data through a serial communication interface (SCI) when the host machine sends downstream data message correspondingly needed by each slave machine once, the slave machine begin to send upstream data message after a certain time interval, a next slave machine begin to send upstream data message after same time interval when a last slave machine sends the upstream data message, and the bus communication method is achieved and the like. Only two physical connection lines are used to achieve high-reliability difference connection on the basis possessed by most majority of microprogrammed control units (MCU), simultaneously high-speed real-time requirements can be met, a bus communication problem of an internal module of the device is solved, real-time controllable communication is achieved, complexity of a hardware circuit is reduced, and generality and reliability are strengthened.
Highlights
The bus could be implemented using any kind of micro control unit (MCU) provided with SCI and timer, the demand for MCU hardware is low
The present invention solves the problem of bus communication between internal modules of a device and realizes controllable communication real time performance, reduced hardware circuit complexity as well as enhanced universality and reliability
The synchronization time division multiplexing bus communication method using serial communication interface according to claim 1, characterized in that, the slaves send the up-link data messages in such a manner that after a slave receives data, determine whether the data is host data or not; if the data is not host data, the slave doesn’t process the data and continue to receive data; and if the data is host data, the slave initiates the timer and implements data validation to the received host data; in the case of validation failure the slave turns off the timer and continues to receive data, and in the case of validation success, the slave proceeds to process data; when the timer reaches, the slave sends data message via the SCI
Summary
Bus is commonly utilized as communication channels between the master board and the input or output board in automatic devices. Normal serial or parallel communication manner could not meet requirements of real time communication under strong interference [1,2]. Due to the fact that there is a wide variety of internal bus, such as parallel bus and serial bus, bus formed by FPGA and formed by CPLD, as well as formed by MCU of other types, bus with SPI interface and with SCI interface, as well as with CAN interface or other types of interface, it’s very difficult to develop a bus with desirable simple architecture applicable to the communication between the master board and the input or output board using short and fixed length communication messages, making the requirements for real time communication hard to be achieved [3,4]
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