Abstract
Part I of the paper ( Electr. Power Syst. Res., 26 (1993) 143–147) on this subject has discussed the design aspects and the basis of the improved method for fault distance calculation. This paper deals with the computational aspects and validation of the fault impedance estimation method proposed in Part I. The performance equations of two fault impedance estimation methods that are based on the symmetrical component theory are reviewed. Also discussed are the computational aspects of these two methods. Instruction execution cycles of a TMS-320 digital signal processor are used to determine the computational requirements of the arithmetic operations of the two methods. A comparative study is also given in this paper. Definite computational advantages of the proposed method over the previously suggested methods based on symmetrical component transformation are demonstrated. The proposed method of Part I is validated using numerical examples.
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