Abstract
This paper reports the impacts of NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. off-state currents may be improved by increasing the oxide overetching depth. The on/ off current ratio may be also improved by increasing the oxide overetching depth. The NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing (<; 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. off-state currents can be improved by increasing <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mask</sub> , even when the oxide overetching depth and the gate oxide thickness are changed.
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