Symbolic Analysis of Analog Circuits By Boolean Logic Operations

Abstract

In this brief, the author proposes a novel symbolic analysis method for analog behavioral modeling by Boolean logic operations and graph representation. The exact symbolic analysis problem is formulated as a logic circuit synthesis problem where we build a logic circuit that detects whether or not a given symbolic term is a valid product term from a determinant. The logic circuit is represented by binary decision diagrams (BDDs), which can be trivially transformed into zero-suppressed BDDs (ZBDDs). ZBDDs are essentially determinant decision diagram (DDD) representation of a determinant. The proposed BBD-based method gives the circuit logic interpretation of symbolic terms in a determinant and exploits such logic interpretation during the BDD/DDD construction process. It demonstrates an inherent relationship between symbolic circuit analysis and logic synthesis. It is the first symbolic analysis method that is not based on traditional Laplace expansion or topological methods. Experimental results show the speedup of our new method over the existing flat method and its improved analysis capacity over both existing flat and hierarchical symbolic analyzers