Abstract
Increasing the switching frequency of the power semiconductor devices (PSDs) reduces the size and cost of the passive elements, thereby positively affecting the power density of a high-frequency (HF) power electronic system (PES). To achieve a higher switching frequency of a PES, yet low switching losses, the speed of switching transitions of PSDs need to be increased. However, such fast transitions adversely affect PES performance in terms of electromagnetic interference (EMI) and device stress. Hence, a switching transition control (STC) scheme is developed to create optimality between switching PSDs with higher transitions yet maintaining safe levels of parasitic oscillations, that result from reducing the transition time of these devices. The switching transition control (STC) framework helps the HF PES achieve a target efficiency improvement by controlling the high di/dt and dv/dt regions of a PSD on the fly. Results are shown to validate that this improvement of efficiency is not feasible with a passive gate drive. An HF Ćuk PES using a Cree SiC MOSFET half-bridge module is fabricated for the testing purpose of the STC framework. The STC network is based on a simple switched resistor network, synthesized using high-speed GaN-FETs and built across two generations, Gen-1, and Gen-2. Practical operational issues of the STC network with fast switching GaN-FET in the Gen-1 board are analyzed and are overcome with design modification in Gen-2. The work has ramifications in meeting a system-level goal of an HF WBG PES, like a target efficiency increment, while not deteriorating the EMI performance and PSD stress levels that result due to parasitic oscillations in such PES.
Highlights
To reduce power electronic system (PES) losses while increasing power densities, the switching transitions of the power semiconductor devices (PSDs) need to be significantly improved as is evident from the recently used WBG PSDs like GaN-FETs and SiC FETs [1]–[7]
Increasing the switching transitions of these new generation devices to decrease the switching losses using fixed gate drive results in non-optimal performance resulting in excessive device stress and electro-magnetic interference (EMI)
Instead of reduced switching losses, these oscillations increase the V-I overlap at the turn-on switching transition even further, resulting in decreased PES efficiency. These oscillations lead to unstable PES gate drive operation, which does not let the PES operate across a wide operating range. In such HF PES, where there is a need of optimality between switching losses and device stress/ oscillations, a switching transition control scheme, as shown in Figure 1, can be synthesized
Summary
To reduce PES losses while increasing power densities (by increasing switching frequencies), the switching transitions of the PSDs need to be significantly improved as is evident from the recently used WBG PSDs like GaN-FETs and SiC FETs [1]–[7]. The literature [13], [15] propose switched resistor-based gate drive modulation to improve the current and voltage transitions of SiC PSDs and achieve controllability and performance optimization in terms of EMI and switching losses. Contrary to the prevalent approaches, which either use complicated mixed-signal schemes or performs a less granular operation, this manuscript delineates a switching transition control (STC) framework using a simple switched resistive based active gate drive. The scheme is easy to synthesize with the increased reliability of high-speed GaN devices and their drive techniques that can switch a resistor with enormous speed without the need for integrated ASICs [19] or complicated mixed-signal schemes[14], [16] It uses the most common industrial-scale processor, F28379D, to realize the circuit without any significant computational burden or complex control[14], [16].
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