Switching speed enhancement of the LDMOSFETs using partial-SOI technology

Abstract

SOI could be the future technology for power integrated circuits (PICs) due to its effective isolation and low leakage currents. Conventional SOI power devices, however, suffer from a reduced breakdown voltage and self-heating effects. To overcome these problems while still maintaining good isolation between the low power CMOS circuits and the high power cells, we proposed partial SOI (PSOI) technology (Udrea et al., Proc. IEEE Int. SOI Conf., p. 102, 1997). PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. In particular, one of the key structures for high voltage, high frequency applications is the LDMOSFET. Compared to the standard junction isolation (JI) LDMOSFET, the SOI-LDMOSFET has a larger drain-substrate capacitance (C/sub dsub/) resulting from the use of the SOI substrate, which has been shown to critically influence the switching speed of the device. It is remarkable to find that PSOI technology for power LDMOSFETs, in addition to increased breakdown and reduced self-heating, is capable of giving a very low C/sub dsub/ compared to their SOI and JI counterparts, resulting in the shortest turn-off time. This makes PSOI technology very attractive for high speed power circuits.