Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges

Abstract

In this work performance investigation of three different Double Gate n-type TFET architectures i.e. Dual material Gate (DMG) TFET, Hetero-Dielectric (H-D) TFET and Dual Material Hetero-Dielectric (DMG H-D) TFET has been performed for Digital Circuit Applications. Moreover, a comparative study among these three aforementioned device architectures has been made in terms of performance metrics such as Total gate Capacitance (C gg ), Miller capacitance (C gd ), fall propagation delay (t pHL ) and peak overshoot voltage (V p ). In this regard, exhaustive simulations have been done through Atlas Device Simulator. Furthermore, the impact of metal gate (M1) work function and length L 1 variation over device switching characteristics has also been observed. Impact of Interface oxide charges (positive and negative) on the transient behavior, threshold voltage, I on , I off , I on /I off has also been studied for all three device architectures. It has been investigated that DMG H-D TFET which is the proposed architecture outperforms other devices i.e. DMG TFET and H-D TFET in terms of comparatively lower value of t pHL , V p and miller capacitance C gd .