Switching activity estimation under real-gate delay using timed Boolean functions

Abstract

A probabilistic method to estimate the switching activity of a combinational circuit under a real-gate delay model considering temporal, structural and input pattern dependencies is introduced. It is proved that the switching activity evaluation problem is reduced to the zero-delay problem at specific time instances. A mathematical model based on Markov stochastic processes, which describes the temporal and spatial correlation in terms of the associated zero-delay parameters, is presented. To handle the influence of time on glitch generation, the theory of the timed Boolean function (TBF) is adopted. Additionally, an algorithm to evaluate the switching activity at specific time instances using TBF-ordered binary decision diagrams (TBF-OBDDs) is given. Comparative study of benchmark circuits demonstrates the accuracy and efficiency of the proposed method.