Switching activity analysis and pre-layout activity prediction for FPGAs

Abstract

It is well-known that dynamic power dissipation in digital CMOS circuits depends linearly on switching activity. In this paper, we study switching activity in a commercial FPGA and propose a novel approach to pre-layout activity prediction. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). Low-power synthesis and early power estimation are typically done on the basis of zero delay activity values, with the assumption that such values correlate well with routed delay activity values. We investigate whether this assumption is valid for FPGA technologies, where critical path delay is often dominated by interconnect delay. We then present an approach for early prediction of routed delay activity values. Our approach is novel in that it estimates each net's routed delay activity using only zero or logic delay activity values along with structural and functional properties of a circuit. Results show that in comparison with zero or logic delay activity values, the predicted activity values are substantially more representative of routed delay activity values.