Switched current circuit using fixed gate-potential transistor and automatic tuning circuit

Abstract

Clock feedthrough (CFT) error is one of the most important problems for switched current (SI) circuits. This paper proposes a SI circuit which can reduce CFT error drastically. The proposed circuit will theoretically reduce both signal-dependent and independent errors by using CMOS switches under a fixed and appropriate bias. Although conventional circuits based on a similar idea need operational amplifiers or additional capacitors, our proposed circuit requires only MOSFETs. The proposed circuit can reduce CFT current with less power consumption and chip area compared to those of conventional circuits. An automatic tuning circuit, which controls the gate potential appropriately, is also proposed. Simulation results demonstrate the effectiveness of the proposed circuits. © 1999 Scripta Technica, Electr Eng Jpn, 126(3): 21–29, 1999