Switch Design for Soft Interconnection Networks

Abstract

Soft on-FGPA interconnection networks are gaining increasing importance since they simplify the integration of heterogeneous components and parallelize, at the same time, the communication among the modules of the system. The switches are the basic building blocks of such networks, and their design critically affects the performance of the whole system. The way data traverse each switch is governed by the operation of the arbiter and the crossbar’s multiplexers that need to be efficiently mapped on the FPGA fabric. The LUT mapping of wide multiplexers has been well investigated, either by enhancing the features of the corresponding mapping algorithms or by fully exploiting the structure and the additional features of the FPGA logic blocks. However, the combined mapping of an arbiter and a multiplexer as a whole to the programmable logic and interconnect of an FPGA has not been sufficiently explored. This chapter aims at bridging this gap; we will first present and compare the traditional implementations that are based on separate allocator and crossbar modules, and then we will expand the design space by presenting new soft macros that can handle allocation and multiplexing concurrently.