Abstract
In this paper, a new version of very large scale integration (VLSI) layouts compaction problem is considered. Bar visibility graph (BVG) is a simple geometric model for VLSI chip design and layout problems. In all previous works, vertical bars or other chip components in the plane model gates, as well as edges, are modeled by horizontal visibilities between bars. In this study, for a given set of vertical bars, the edges can be modeled with orthogonal paths known as staircases. Therefore, we consider a new version of bar visibility graphs (BsVG). We then present an algorithm to solve the s-visibility problem of vertical segments, which can be implemented on a VLSI chip. Our algorithm determines all the pairs of segments that are s-visible from each other.
Highlights
Visibility problems are very popular in many application areas, in very large scale integration (VLSI) circuit layout
They studied the problem of computing rectangle visibility graphs (RVGs) of a set of vertical bars
In this study, we considered a new version of the VLSI chip design problem: the problem of finding the bar s -visibility graph (BsV G) of a set of given vertical bars in the plane
Summary
Visibility problems are very popular in many application areas, in very large scale integration (VLSI) circuit layout. Bar visibility graph (BVG) is a simple geometric model for VLSI chip design and layout problems [1,2,3,4]. In this model, vertical bars in the plane model gates, other chip components, and edges are modeled by horizontal visibilities between bars. The problem of determining the visible pairs of n given vertical segments in the horizontal visibility model was studied by Lodi et al in 1986 [5]. In 2015, Carmi et al studied the problem of computing the visibility graph of a set of vertical segments (known as walls). There is an edge between two walls if, and only if, they are weakly visible to each other
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