Abstract
In digital signal processing (DSP), the power consumption is more so, to decrease power and latency without affecting the other parameters, and mostly, the filters are designed using finite state machine (FSM). This paper gives a view of the multiplier architectures and its design issues for the expected level of performance. Literature states that the FSM approach is also a good choice in designing the multiplier architectures. In this paper, various design approaches are also described with the HDL modeling language, like in Verilog HDL, in building efficient multipliers. High-speed multipliers like Vedic multipliers are good in terms of speed and are considered as fastest and low-power multipliers.
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