Abstract
The continuing increase in functional requirements of modern hardware designs means the traditional functional verification process becomes inefficient in meeting the time-to-market goal with sufficient level of confidence in the design. Therefore, the need for enhancing the process is evident. Machine learning (ML) models proved to be valuable for automating major parts of the process, which have typically occupied the bandwidth of engineers; diverting them from adding new coverage metrics to make the designs more robust. Current research of deploying different (ML) models prove to be promising in areas such as stimulus constraining, test generation, coverage collection and bug detection and localization. An example of deploying artificial neural network (ANN) in test generation shows 24.5× speed up in functionally verifying a dual-core RISC processor specification. Another study demonstrates how k-means clustering can reduce redundancy of simulation trace dump of an AHB-to-WHISHBONE bridge by 21%, thus reducing the debugging effort by not having to inspect unnecessary waveforms. The surveyed work demonstrates a comprehensive overview of current (ML) models enhancing the functional verification process from which an insight of promising future research areas is inferred.
Highlights
Design verification is the continuous process of checking whether a design meets the specification or not
Some of the sentences that resulted in meaningful results included “Faster verification closure using machine learning”, “Accelerating functional verification coverage closure using Machine learning algorithms”, “Verification machine learning assertions”, “Machine learning in functional verification thesis”, “Functional verification neural networks”, “Machine learning hardware verification” and “Speeding up functional verification machine learning”
HDL testbenches to verify the functional aspect of the design; while reaching the same percentage of the planned coverage groups
Summary
Design verification is the continuous process of checking whether a design meets the specification or not. Testing all design state space is impractical [1] and the approach of writing independent test vectors to verify each state becomes highly infeasible given that about 70% of overall design activity is consumed by verification activities [1]. A verification plan is formed with the design features to cover and input stimulus is randomly generated and fed to the design under test DUT with constraints to exercise the main state space. For areas that are hard-to-hit, directed tests are written to trigger them [2]. This process of writing the constrained random and directed tests keeps the engineers busy and if improved, will free-up valuable time to be used for adding more features to be covered in the verification plan
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