Survey of Shared Register File design for Unified Shader Array in GPUs

Abstract

Unified Shader Array (USA) is the computing core of the Unified Shader Array Graphic Processing Unit (GPU), and the shader cores is the basic shader Unit of the Unified Shader Array. In order to support the large-scale thread-level parallelism of GPU, a large number of streaming processors composed of shader cores are set in GPU. The streaming processors (SP) can enable GPU to implement thread-level parallelism in the way of Single Instruction Multiple Data (SIMD) or Single Instruction Multiple Threads (SIMT). At the same time, in order to reduce the cost caused by context switching, GPU deployments a large scale of register file resources at the bottom level for the use of the streaming processor. So the management and use of register file is of great significance to the performance of GPU. The unique register file for each shader cores in the traditional GPU simplifies the register management hardware, but at the cost of insufficient register utilization. It will cause the disadvantage of limited size of shader cores. This paper introduces the current research status of various technologies at home and abroad from the aspects of register file sharing, high resource utilization and low power consumption.