SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process

Abstract

Speeded Up Robust Feature(SURF) is widely used in computer vision applications. In many recent applications like mobile devices and vision sensor network, it is extremely difficult to meet both the performance and power consumption requirements of SURF implementations, especially for CPU, GPU, DSP or FPGA based solutions. In this paper, the SURF algorithm is simplified and optimized for hardware implementation. To increase the throughput, procedures like orientation assignment and descriptor extraction are re-organized while maintaining enough accuracy; the memory accesses have also been improved to increase the bandwidth and reduce repeated data accesses; the workload of each stage in the pipeline is analyzed and balanced to reduce the pipeline bubble. Furthermore, a method called Word Length Reduction (WLR) is adopted to compress the integral image, which reduces the on-chip memory by 40%. In addition to that, the corresponding power consumptions are reduced significantly. The Simplified SURF is implemented onto a 3.4×4.0 mm2 chip called SURFEX using TSMC 65nm process. The chip is able to process 57 frames of 1080p(1920×1080) video per second with a 200MHz working frequency while dissipating 220mW. This throughput is 6 times of the ones reported in the latest literatures and the power consumption is less than half of the most outstanding implementations.