Surface Passivation of Thin Silicon Solar Cells Using Silicon-on-Insulator Wafer

Abstract

Solar cells with various cell thicknesses were fabricated using silicon-on-insulator (SOI) wafers, and effects of applied bias voltages (V B) at the SOI layer/SiO2 back interface on cell performance were investigated. A surface passivation effect was obtained by applying negative V B to accumulate holes at the interface. Both open-circuit voltage (V oc) and short-circuit current were improved by applying negative V B. This effect becomes more dominant for thinner cells. V oc of 20- and 50-µ m-thick cells at V B=-15 V increased compared to that of a 100-µ m-thick cell. Surface recombination velocity (S) was estimated from the dependence of internal quantum efficiency on cell thickness. It was found that S decreased from about 106 to 104 cm·s-1 when V B changed from 0 to -15 V. The improvement of cell performance by V B was due to this reduction in S. Therefore, the surface passivation by applying bias voltages is noted as an important technique to realize high-efficiency thin silicon solar cells.