Abstract
Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.
Highlights
When the capacitor is designed properly with control lines weakly coupled to an external circuit, dielectric surface loss from the superconductor and substrate is the dominant mechanism of energy loss
The total loss tangent for these thin layers is given by Σpi tan δi, where surface interface type i has loss tangent tan δi and participation ratio of the stored energy
The solutions were extended to the useful limit where the thin surface oxide is less than the metal film thickness (0.1 μm), and less than the typical film size (100 μm)
Summary
Quantum computers are made from quantum bits, which have natural sources of noise and dissipation that produce errors in quantum gates. Decreasing these errors increases the size and complexity of quantum algorithms that can be run on a quantum computer. Qubit errors are often limited by the rate of energy decay from loss mechanisms. The Josephson junction and the capacitance are designed to be separate physical entities, as illustrated, and can be separately optimized. As for any surface loss mechanism, it has been found experimentally that increasing the size of this capacitor lowers the net effect of the surface loss on the qubit device[3]
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