Surface, Interface and Valence Band of Ultra-Thin Silicon Oxides

Abstract

In 1987, silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) with gate oxide film thickness of 3.3 nm were shown to operate at liquid nitrogen temperature.[1] As a result of continuing progress in microfabrication technology since that time, MOSFETs with gate oxide film thickness of 1.5 nm were shown to operate at room temperature[2] and the fabrication of 1 Gbit dynamic random access memory (DRAM) was reported.[3,4] The mass production of 1 Gbit DRAM using MOSFETs with gate oxide film thickness of about 5 nm must be realized at the beginning of the next century. In this case the thickness of one-molecular-layer of SiO2 corresponds to 6% of gate oxide film thickness. Therefore, it is necessary to control the formation of SiO2 and SiO2/Si interface on an atomic scale by improving the cleanliness and flatness of Si surfaces before the oxidation The control of oxide formation on an atomic scale is important for the formation of high quality SiO2/Si interfaces for future metal-oxidesemiconductor (MOS) technology.[5]