Abstract

In this paper we present a process of forming monolithic GaN surface from an ordered nanowire array by means of material redistribution. This process, referred to as reformation, is performed in a conventional MOVPE crystal growth system with the gallium supply turned off and allows a crystal nanostructure to change shape according to differences in surface energies between its facets. Using reformation, coalescence may proceed closer to thermodynamic equilibrium, which is required for fabrication of high-quality substrate material. Scanning probe techniques are utilized, complemented by cathodoluminescence and electron microscopy, to investigate structural and electrical properties of the surface after reformation, as well as to assess densities, location, and formation of different types of defects in the GaN film. Spatial variations in material properties such as intrinsic majority-carrier types can be attributed to the radical changes in growth conditions required for sequential transition between nanowire growth, selective shell growth, and reformation. These properties enable us to assess the impact of the process on densities, locations, and formation of different types of dislocations in the GaN film. We find a fraction of the nanowires to comprise of a single electrically neutral edge dislocation, propagating from the GaN buffer, while electrically active dislocations are found at coalesced interfaces between nanowires. By decreasing the mask aperture size and changing the nucleation conditions the prevalence of nanowires comprising edge dislocation was significantly reduced from $6%$ to $3%$, while the density of interface dislocations was reduced from $6\ifmmode\times\else\texttimes\fi{}{10}^{8}$ to $4\ifmmode\times\else\texttimes\fi{}{10}^{7}\phantom{\rule{4pt}{0ex}}{\mathrm{cm}}^{\ensuremath{-}2}$. Using a sequential reformation process was found to create inversion domains with low surface potential N-polar regions in an otherwise Ga-polar GaN film. The inversion domains were associated with pinned dislocation pairs, and were further confirmed by selective wet etching in NaOH. This lateral polarity inversion was thoroughly eliminated in samples formed by a continuous reformation process. These results reveal a path and challenges for growing GaN substrates of superior crystal quality through nanowire reformation.

Highlights

  • Radio frequency (RF) and power electronics both stand at tipping points where silicon technology is running out of steam

  • The lattice size and thermal expansion coefficient of these crystals are different from Gallium nitride (GaN), creating a material mismatch which is the main source of extended defect networks, mainly threading dislocations (TDs), in heteroepitaxial GaN substrates

  • High densities of TDs limit device performance by Coulomb scattering, increased nonradiative recombination, and vertical leakage paths [3,4,5,6,7] resulting in reduced device breakdown voltage [8], the latter providing a particular challenge to the development of GaN vertical device architectures

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Summary

Introduction

Radio frequency (RF) and power electronics both stand at tipping points where silicon technology is running out of steam. For other semiconductors of technological importance, high quality commercial substrates are almost exclusively grown from melt, most often by the Czochralski liquid phase epitaxy technique. This method is not viable for GaN, which requires extreme conditions, with the best estimate known to date being 6 GPa and 2600 K to form a congruent melt [2]. The lattice size and thermal expansion coefficient of these crystals are different from GaN, creating a material mismatch which is the main source of extended defect networks, mainly threading dislocations (TDs), in heteroepitaxial GaN substrates. High densities of TDs limit device performance by Coulomb scattering, increased nonradiative recombination, and vertical leakage paths [3,4,5,6,7] resulting in reduced device breakdown voltage [8], the latter providing a particular challenge to the development of GaN vertical device architectures

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