Suppression of Si Cavities at the SiC/Si Interface during Epitaxial Growth of 3C-SiC on Silicon-on-Insulator

Abstract

Epitaxial growth of 3C-SiC on silicon on insulator (SOI) has certain advantages over the deposition on Si wafers. The existing buried oxide layer isolates the SiC overgrown from the Si substrate preventing the leak current through the Si substrate even at high temperatures. During the SiC deposition, SOI is more sensitive in the formation of cavities in the Si at the SiC/Si interface than in bulk Si, because only the thin Si overlayer is the reservoir for the Si supply during carbonization process. The evolution of cavities in the Si overlayer (SOL) was studied vs. carbonization process, SiC growth rate, SOL thickness, and thickness of the 3C-SiC overgrown. There are three main reasons for the formation of the cavities: (i) the consumption of Si from the Si overlayer for the formation of the SiC buffer layer during the carbonization process, (ii) the out-diffusion of Si through the 3C-SiC overgrown during deposition of SiC, and (iii) the balling up of the Si at the edges of the cavities due to the instability of the system at high temperatures. Knowing the mechanisms responsible for the formation of the cavities, the SiC deposition conditions were modified in order to suppress cavities. Thus the deposition temperature was reduced to 1200°C, as reactive gas was used methylsilane, finally fast deposition rate in the early stage of growth, followed by the standard rate as the growth advances, significantly suppresses the cavities giving 3C-SiC comparable with the standard 3C-SiC grown under a one-step process. © 2000 The Electrochemical Society. All rights reserved.