Suppression of parasitic electron injection in silicon-oxide-nitride-oxide-silicon-type memory cells using high-k capping layers

Abstract

In this article the application of thin high-k dielectrics as capping layers on oxide/nitride/oxide memory stacks with respect to suppression of electron injection from the gate electrode during erase operation is investigated. The authors demonstrate that hafnium silicate layers, with a dielectric constant of 17, as thin as 1nm of physical thickness can clearly reduce electron injection and thereby prevent erase saturation. In theory, tunneling currents will be more strongly suppressed with increasing k values when keeping the equivalent oxide thickness constant. Therefore, the prevention of erase saturation will be further improved. However, titanium oxide as capping layer, which has a dielectric constant of 60, exhibits inferior erase performance due to a strong electron injection by field-enhanced thermal emission of electrons. This Poole-Frenkel conduction mechanism takes place along trapping sites 0.32eV below the conduction band in the titanium dioxide. While the application of high-k materials can efficiently suppress erase saturation due to tunneling currents, this effect can be diminished by leakage currents along shallow trapping sites which occur in high-k dielectrics.