Suppression of Interface State Generation in Si MOSFETs with Biaxial Tensile Strain

Abstract

In this letter, we experimentally investigate the interface state generation behaviors in biaxial tensile strained-Si (s-Si) MOSFETs. It is found that s-Si MOSFETs exhibit a much smaller interface state generation rate than bulk-Si MOSFETs, under the same gate current. Our results show that such robustness of the s-Si MOS interface cannot be explained by the decrease in the substrate hole current flowing through the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface, which has widely been recognized as an origin of the interface state generation. Our results indicate that the mechanism may be attributed to the smaller SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface roughness in s-Si devices, which has previously been reported.