Suppression of Edge Effect Induced by Positive Gate Bias Stress in Low-Temperature Polycrystalline Silicon TFTs With Channel Width Extension Over Source/Drain Regions

Abstract

This study demonstrated that the edge effect induced by positive gate bias stress (PBS) was effectively eliminated by applying channel width extensions over source/drain regions in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). After PBS, a stress-induced hump current in subthreshold region is observed and is caused by the charge trapping into parasitic transistors along the channel width edges. This phenomenon is attributed to carrier injection occurring along the width edges since a high electric field is located at that region, where lots of defects are generated due to the definition of the active area during the etching process. In this study, we show that the degradation in electrical characteristics during the gate bias operation resulted from the edge effect can be eliminated when the TFT devices utilize the channel width extension in the active layer. Electrical measurements, numeral calculations, and a TCAD electrical simulation confirm that this geometry, which includes a channel extension along the width direction, can dramatically reduce the carrier injection at the edges even though high electric field is mainly located at the width edges during gate bias operation.