Suppressing random dopant-induced fluctuations of threshold voltages in semiconductor devices

Abstract

This article introduces a robust and computationally efficient technique for the design of fluctuation-resistant structures (fault-tolerant) semiconductor devices. This technique can be applied to the computation of the doping profiles that minimize the intrinsic variations in various parameters induced by random dopant fluctuations. The technique is based on the evaluation of doping sensitivity functions, which are defined as elements of the space adjoint to the space of square integrable functions generated by all possible doping variations. The optimized doping profiles are computed by minimizing the standard deviation of fluctuations of different parameters, and constraints are taken into consideration by using the Lagrange multiplier method. The technique introduced here can be applied to any semiconductor device, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), silicon-on-insulator (SOI) devices, and fin field-effect transistors, and can be used in the framework of any transport model. The technique is applied to the minimization of the random dopant-induced fluctuations of threshold voltages in 25 nm channel length MOSFETs and double-gate fully depleted SOI devices. It is shown that, by carefully designing the doping profiles, random dopant-induced fluctuations can be suppressed between 16% in the case of constrained optimization and 35% in the case of unconstrained optimization for devices with channel lengths smaller than 25 nm. Analytical equations are derived for the optimum doping profiles that minimize the effects of random dopant fluctuations on the threshold voltage in MOSFETs. It is shown that, in both long-channel and short-channel devices, the size of the undoped region should be at least 14 of the width of the depletion region in order to suppress efficiently the random dopant-induced fluctuations.