Suppressing Layout-Induced Threshold Variations by Halo Engineering

Abstract

When creating source/drain regions of a MOSFET transistor, the implants introduce crystal damage. During subsequent activation annealing, the implant damage serves as a source of silicon interstitials that create dopant transient-enhanced diffusion (TED). The amount of TED is determined by the source/drain area and by the proximity of STI boundary, where interstitials recombine. Different amount of TED, experienced by transistors with different shapes and sizes of their source/drain area, lead to the difference in dopant diffusion in the channel/halo, and the corresponding variation of the threshold voltage. Depending on specific combination of layout and process flow, the MOSFET threshold voltages can either increase or stay flat or decrease with the distance from the channel to the STI. For each set of design rules/technology node, it is possible to design the halo implants such that the threshold sensitivity is close to flat and therefore eliminate layout sensitivity of the threshold voltage.