Abstract
This paper presents a voltage reference circuit, operating in sub-threshold region. The circuit is made tolerant to temperature and supply variations. The temperature tolerant behaviour of reference circuit is achieved by incorporating the difference of gate to source voltages of high Vth and standard Vth transistors. The bias voltage for the reference circuit is generated using a bias circuit and made temperature insensitive using a variable load with digital trimming technique. The circuit is simulated with 0.18 \(\upmu \)m CMOS models. Reference voltage variation with supply is 6.25 mV/V, variation with temperature is 9.37 uV/C in 0 \(^\circ \)C to 100 \(^\circ \)C temperature sweep. The power consumption is 50 nW at room temperature with 0.8 V as supply voltage. Power Supply Rejection Ratio (PSRR) of the proposed circuit at room temperature with 0.8 V supply is simulated to be −72 dB at 100 Hz and −23 dB at 1 MHz.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
