Superior Spike Annealing Performance in 65nm Source/Drain Extension Engineering

Abstract

To meet the requirements of smaller devices while still maintaining high performance, it is necessary to form shallow source/drain extensions with high activation. For 65nm devices, reducing the peak width of spike annealing will enhance device performance. Two RTP tools were compared by 65nm device performance with different residence times (1.4s and 1.85s). Spike anneal thermal profile of the shorter residence time (1.4s) demonstrated 4% reduction in Cov and improved Vt roll-off based on device data. The improvement is due to the efficient suppression of lateral diffusion in source/drain extensions. RTP A demonstrates this improvement while retaining the same I on /I off performance as delivered in the larger thermal budget spike anneal system. In this paper we show that shorter residence time (peak width) is required to improve ultra-shallow junction performance in 65nm devices as characterized by I on /I off , and Vt parameters.