Abstract

The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQ-based architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment.

Highlights

  • ON SFQ LOGIC TECHNOLOGYSFQ circuits utilize a small-voltage pulse as an information carrier, which can be stored as a single magnetic flux quantum (SFQ) in a superconductor ring [Figure 1(a)]

  • We are running out of effective options to improve the performance of CMOS-based computer systems while maintaining their power and temperature budgets.[1]

  • If there is a large difference between the arrivals, the clock frequency decreases because both inputs must arrive at the destination gate in the same clock cycle period

Read more

Summary

Superconductor Computing for Neural Networks

The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and lowpower switching characteristics of superconductor devices. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). We developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We believe that now is the right time to exploit emerging device technologies with significant potential and make a serious effort to improve their feasibility. The superconductor single-flux-quantum (SFQ) logic family[2] has emerged as a highly promising solution for the postMoore era. SFQ technology, which utilizes superconductor devices operating at 4K, has significant potential for both high performance and energy efficiency. SFQ logic gates use low-voltage impulseshaped signals for their operations and achieve the ultrafast ($ 10À12 s) and low-energy ($ 10À19 J)

Published by the IEEE Computer Society
ON SFQ LOGIC TECHNOLOGY
Network Unit for Systolic Array
Processing Element With WeightStationary Dataflow
SIMULATION FRAMEWORK
Architectural Bottlenecks and Design Implications
Findings
IMPACTS AND PROSPECTIVE
Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call