Super-junction LDMOST on a silicon-on-sapphire substrate

Abstract

A super-junction lateral double diffused MOST (SJ-LDMOST) in silicon-on-sapphire technology, targeting power integrated circuits (PICs), is proposed, implemented and characterized. The proposed structure eliminates "substrate-assisted-depletion" effects in lateral SJ devices thus achieving charge compensation between the n and p SJ-pillars as well as a uniform electric field distribution in the drift region in the off-state. Three-dimensional (3-D) simulations of the device, using realistic aspect ratios for the SJ-pillars, indicate that a significant reduction in specific on-resistance for a given breakdown voltage can be achieved as compared to conventional reduced surface field (RESURF) devices. Experimental devices were implemented using a seven mask CMOS compatible process. Fabricated SJ-LDMOSTs with a drift region length of 66 /spl mu/m and a pillar aspect ratio of 1.2 /spl mu/m/0.7 /spl mu/m (width/height) exhibit a specific on-resistance of 0.82 /spl Omega/.cm/sup 2/ and a breakdown voltage (BV) ranging between 500 and 600 V corresponding to less than 8.5% charge imbalance in the pillars.